{"dataType": "CVE_RECORD", "cveMetadata": {"state": "PUBLISHED", "cveId": "CVE-2026-50719", "assignerOrgId": "8254265b-2729-46b6-b9e3-3dfca2d5bfca", "assignerShortName": "mitre", "dateUpdated": "2026-08-19T13:47:58.178Z", "dateReserved": "2026-06-05T00:00:00.000Z", "datePublished": "2026-08-19T00:00:00.000Z"}, "containers": {"cna": {"providerMetadata": {"orgId": "8254265b-2729-46b6-b9e3-3dfca2d5bfca", "shortName": "mitre", "dateUpdated": "2026-08-19T13:47:58.178Z"}, "descriptions": [{"lang": "en", "value": "The Ingenic T41, and probably also T32, T40, and A1 SoC boot ROMs parse and execute an attacker-controlled init table from the SPL header before checking the secure boot state and before invoking signature verification. The init table parser supports full-address 32-bit write operations, allowing modification of SRAM-resident secure boot state prior to the verification decision. An attacker with physical write access to boot media can inject an init-table entry that disables the secure boot check, causing the ROM to accept unsigned or modified first-stage boot code. This has been hardware-validated on a secureboot-enabled T41 device; ROM analysis confirms closely related behavior on T32, T40, and A1."}], "affected": [{"vendor": "n/a", "product": "n/a", "versions": [{"version": "n/a", "status": "affected"}]}], "references": [{"url": "https://opensensor.io/security/ingenic-t32-t40-t41-a1-init-table-bypass"}], "problemTypes": [{"descriptions": [{"type": "text", "lang": "en", "description": "n/a"}]}]}}, "dataVersion": "5.2"}

{}

{"affected": [{"affectedData": [{"product": "n/a", "vendor": "n/a", "versions": [{"status": "affected", "version": "n/a"}]}], "source": "[email protected]"}], "cveTags": [], "descriptions": [{"lang": "en", "value": "The Ingenic T41, and probably also T32, T40, and A1 SoC boot ROMs parse and execute an attacker-controlled init table from the SPL header before checking the secure boot state and before invoking signature verification. The init table parser supports full-address 32-bit write operations, allowing modification of SRAM-resident secure boot state prior to the verification decision. An attacker with physical write access to boot media can inject an init-table entry that disables the secure boot check, causing the ROM to accept unsigned or modified first-stage boot code. This has been hardware-validated on a secureboot-enabled T41 device; ROM analysis confirms closely related behavior on T32, T40, and A1."}], "id": "CVE-2026-50719", "lastModified": "2026-08-19T14:17:31.977", "metrics": {}, "published": "2026-08-19T14:17:31.977", "references": [{"source": "[email protected]", "url": "https://opensensor.io/security/ingenic-t32-t40-t41-a1-init-table-bypass"}], "sourceIdentifier": "[email protected]", "vulnStatus": "Received"}

{}

{"created": "2026-08-19T20:00:05.087943+00:00", "title": "Secure Boot Bypass via Erroneous Init Table Order in Ingenic T41/T32/T40/A1 SoCs", "updated": "2026-08-19T20:00:05.087949+00:00", "vendors": [], "weaknesses": ["CWE-287"]}